This paper presents Augmented Monkey Optimization Algorithm (AMOA) applied to solve optimal reactive power problem. Communal behaviour of monkeys has been utilized to model the algorithm. Normally, group monkeys assess the distance from the source to food for foraging behaviour. Local leader renews its most excellent location inside the group, when the food source is not rationalized then the group will start probing in different directions for the food sources. Two most important control parameters are Global Leader Limit (GLlimit) and Local Leader Limit (LLlimit) which give appropriate way to global and local leaders correspondingly. Levy flight has been intermingled in the algorithm to enhance the search ability. Proposed AMOA accelerates the exploitation ability that has been tested in standard IEEE 14, 30, 57, 118, 300 bus test systems. The simulation results show the projected algorithm reduced the real power loss comprehensively.

This work presents Amplified Black Hole Algorithm (ABHA) for solving optimal reactive power problem. In the projected approach ABHA, Gravitational Search Algorithm (GSA) is merged with Black Hole Algorithm (BHA). power loss Reduction is the key objective in the proposed work. The gravitational force between stars and the progression of stars to the black hole is attuned while explore the solution space. Assumption made that heavy objects are stars in a gravitational system, which become black holes and the exploitation of GSA is enhanced. During the progression of the projected algorithm, the radius of the black hole diminishes and more objects are included, which assist to stop early convergence. To improve the exploration and exploitation, stars gravity information has been utilized. During the progression of the projected algorithm, the radius of the black hole diminishes, and more objects are included, which assist to stop early convergence. Some of the most excellent objects turn out to be the black hole, affect other objects by their sturdy gravity. The other objects are alienated into two groups: Heavy agents and light agents. Proposed ABHA has been tested in standard IEEE 14, 30, 57, 118, 300 bus test systems and simulation results show the projected algorithm reduced the real power loss comprehensively.

Today power consumption is considered to be one of the important issues. Therefore, its Reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in cache memories. There is a direct relationship between power consumption and replacement quantity made in cache. The less the number of replacements is, the less the power consumption is. In this paper, a mechanism was proposed a mechanism to reduce power consumption using full associative organization and layered replacement algorithm. In this scheme, all cache blocks were divided into three layers. Final layer used FIFO replacement algorithm and middle layer used random replacement algorithm. Also first layer used LRU replacement algorithm. Simulation results were shown using tools written by VB language that in the proposed plan the number of replacement was less than 8-way associative using LRU replacement algorithm.

One of the most common solutions to deal with the power quality issues of electrical railway systems is employing Railway power Conditioner (RPC). In the conventional mode of operation, the RPC power rating deployed in every Traction power Substation (TPS) is significantly large. This paper mainly focuses on the power rating Reduction of RPC through presenting of a novel combinatorial compensation method. The inductive and capacitive switching algorithm retrieved from Steinmetz circuit lead to additional auxiliary balance in sequential TPS which declines the RPC function in elimination of the Negative Sequence Current (NSC). The proposed method can reduce the voltage over Sectioning Posts (SP), DC-link operation voltage, back-to-back (B2B) converters rating and installation costs. The accuracy and effectiveness of the proposed strategy are confirmed via simulation results obtained by MATLAB/SIMULINK program.

In this paper, dynamic comparators structure, by employing two methods for power consumption Reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed comparators have low consumption thanks to power Reduction methods. They have the ability for adjusting the offset. The comparators consume 14. 3 and 24 μ W at 100 MHz, which is equal to 3. 7 and 11. 8 fJ. The comparators are designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μ m2, respectively.